Architectures for Multiplication in Galois Rings

This project investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer. The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can.

Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.


In coding theory results and structures from abstract algebra are used extensively.Many of the most popular coding methods draw advantage of the use of finite, or Galois, fields for their descriptions, since they are linear in this context. These codes include cyclic codes, Reed-Solomon codes and BCH codes.

For a description of these codes. Such codes may be used for error detection and correction in for example telecommunications and CD players, and are often implemented in hardware. Since they all use the finite field structure there exists much research on how to implement elementary finite field operations in hardware, most notably VLSI.

Not so long ago it was shown that some codes that were previously known not to be linear over Galois fields actually were linear, cyclic codes over Galois rings. These codes include the Kerdock and Preparata codes. The Galois rings have much in common with the Galois fields, but there are also differences. For example division is not generally possible in Galois rings.

Nonetheless, their similarities imply that it could be possible to take the implementations of operations in Galois fields, make small adjustments to them and use for Galois rings, without having to do all the research over again for rings instead of fields. That is precisely what we will strive to do in this thesis.
Source: Linköping University
Author: Abrahamsson, Björn

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